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INTEGRATED CIRCUITS
PCA9560 Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
Product data Supersedes data of 2002 May 24 2003 Jun 27
Philips Semiconductors
Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
FEATURES
* 5-bit 3-to-1 multiplexer, 1-bit latch DIP switch * 5-bit external hardware pins * Two 6-bit internal non-volatile registers, fully pin-to-pin compatible * * Selection between non-volatile registers and external hardware * I2C/SMBus interface logic * Internal pull-up resistors on input pin and control signals * Active high write protect on input controls the ability to write to the * * 5 open drain multiplexed outputs * Open drain non-multiplexed output * Internal 6-bit non-volatile registers programmable and readable via * * Multiplexer selection can be overridden by I2C-bus * Operating power supply voltage 3.0 V to 3.6 V * 5 V and 2.5 V tolerant inputs * 0 to 400 kHz clock frequency * ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V * Latch-up testing is done to JESDEC Standard JESD78 which *
exceeds 100 mA. Package offering: SO 20, TSSOP 20 MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I2C-bus External hardware 5-bit value readable via I2C-bus non-volatile registers 2 address pins, allowing up to 4 devices on the I2C-bus pins with PCA9559 Selection between the two non-volatile registers
IDentification code) configuration. It is used to bypass the CPU-defined VID values and provide a different set of VID values to the VRM, if an increase in the CPU voltage is desired. An increase in CPU voltage combined with an increase in CPU frequency leads to a performance boost of up to 7.5%. Lower CPU voltage reduces power consumption. The main advantage of the PCA9560 over the older PCA9559 device in this application is that it contains two internal non-volatile EEPROM registers instead of just one, allowing three independent settings (performance operation, deep sleep mode and deeper sleep mode) instead of only two (performance operation and deep sleep mode). The PCA9560 is footprint compatible and a drop-in replacement for the PCA9559, without any software modifications required. The PCA9560 has 2 address pins allow up to 4 devices to be placed on the same I2C bus or SMBus.
PIN CONFIGURATION
SCL SDA A1 A0 MUX_IN A MUX_IN B MUX_IN C MUX_IN D MUX_IN E 1 2 3 4 5 6 7 8 9 20 VDD 19 WP 18 MUX_SELECT_1 17 NON-MUXED_OUT 16 MUX_OUT A 15 MUX_OUT B 14 MUX_OUT C 13 MUX_OUT D 12 MUX_OUT E 11 MUX_SELECT_0
GND 10
SW00829
Figure 1. Pin configuration
PIN DESCRIPTION
PIN 1 2 3 4 5-9 10 11 12-16 17 18 19 20 SYMBOL SCL SDA A1 A0 MUX_IN A-E GND MUX_ SELECT_0 MUX_OUT E-A NON-MUXED_ OUTPUT MUX_ SELECT_1 WP VDD FUNCTION Serial I2C-bus clock Serial bi-directional I2C-bus data Programmable LSBs of I2C address External inputs to multiplexer Ground Selects MUX_IN inputs or register contents for MUX_OUT outputs Open drain multiplexed outputs Open drain output from non-volatile memory Selects between the two non-volatile registers Active high non-volatile register write-protect input Power supply: +3.0 to +3.6 V
DESCRIPTION
The PCA9560 is a 20-pin CMOS device consisting of two 6-bit non-volatile EEPROM registers, 5 hardware pin inputs and a 5-bit multiplexed output with one latched EEPROM bit. It is used for DIP switch-free or jumper-less system configuration and supports Mobile and Desktop VID Configuration, where 3 preset values (2 sets of internal non-volatile registers and 1 set of external hardware pins) set processor voltage for operation in either performance, deep sleep or deeper sleep modes. The PCA9560 is also useful in server and telecom/networking applications when used to replace DIP switches or jumpers, since the settings can be easily changed via I2C/SMBus without having to power down the equipment to open the cabinet. The non-volatile memory retains the most current setting selected before the power is turned off. The PCA9560 typically resides between the CPU and Voltage Regulator Module (VRM) when used for CPU VID (Voltage
ORDERING INFORMATION
PACKAGES 20-Pin Plastic SO TEMPERATURE RANGE -40 to +85 C ORDER CODE PCA9560D TOPSIDE MARK PCA9560D DRAWING NUMBER SOT163-1 SOT360-1
20-Pin Plastic TSSOP -40 to +85 C PCA9560PW PCA9560 Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging. 2003 Jun 27 2
Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
BLOCK DIAGRAM
PCA9560
WRITE PROTECT
NON-VOLATILE REGISTER 0 6-BIT EEPROM
6 6-BIT 2 to 1 DEMULTIPLEXER LATCH NON-MUXED_OUT NMO
NON-VOLATILE REGISTER 1 6-BIT EEPROM
6
5
8
A0 A1 SCL SDA INPUT FILTER I2C/SMBus CONTROL LOGIC
MUX_OUT_A VDD POWER-ON RESET 3 GND 5-BIT 2 to 1 DEMULTIPLEXER MUX_OUT_C
MUX_OUT_B
MUX_IN_A
MUX_OUT_D
MUX_IN_B MUX_OUT_E
MUX_IN_C
5
MUX_IN_D
MUX_IN_E
MUX_SELECT_1
SELECT LOGIC MUX_SELECT_0 SW00841
Figure 2. Block diagram
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Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
DEVICE ADDRESS
Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9560 is shown in Figure 3. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. The last bit of the slave address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write operation.
MSB 1 0 0 1 1 A1 A0 LSB R/W
CONTROL REGISTER
Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9560, which will be stored in the control register. This register can be written and read via the I2C bus.
D7
D6
D5
D4
D3
D2
D1
D0
SW00954
Figure 4. Control Register
FIXED
HARDWARE SELECTABLE
SW00955
Figure 3. Slave address
CONTROL REGISTER DEFINITION
Following the address and acknowledge bit with logic 0 in the read/write bit, the first byte written is the command byte. If the command byte is reserved and therefore not valid, it will not be acknowledged. Only valid command bytes will be acknowledged. Table 1. Register Addresses D7 0 0 1 D6 0 0 1 D5 0 0 1 D4 0 0 1 D3 0 0 1 D2 0 0 1 D1 0 0 1 D0 0 1 1 REGISTER NAME EEPROM 0 EEPROM 1 MUX_IN TYPE Read/Write Read/Write Read REGISTER FUNCTION EEPROM byte 0 register EEPROM byte 1 register MUX_IN values register
Table 2. Commands D7 1 1 1 1 D6 1 1 1 1 D5 1 1 1 1 D4 1 1 1 1 D3 1 1 1 1 D2 0 1 X X D1 0 0 1 X D0 0 0 0 1 COMMAND MUX_OUT from EEPROM byte 0 MUX_OUT from EEPROM byte 1 MUX_OUT from MUX_IN MUX_OUT from MUX_SELECT2
NOTE: 1. All other combinations are reserved. 2. MUX_SELECT pins select between MUX_IN and EEPROM to MUX_OUT.
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Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
REGISTER DESCRIPTION
If the command byte is an EEPROM address, the next byte sent will be programmed into that EEPROM address on the following STOP condition, if the WP is logic 0. If more than one byte is sent sequentially, the second byte will be written in the other-volatile register, on the following STOP condition. If any more data bytes are sent after the second byte, they will not be acknowledged and no bytes will be written to the non-volatile registers. After a byte is read from or written to the EEPROM, the part automatically points to the next non-volatile register. If the command code was FFH, the MUX_IN values are sent with the three MSBs padded with zeroes as shown below. If the command codes was 00H, then the non-volatile register 1 is sent, and if the command code was 01H, then the non-volatile register 1 is sent.
EEPROM Byte 0 Register
D7
Write Read Default
D6 X 0 0
D5 Non-Muxed Data Non-Muxed Data 0
D4 EEPROM 0 Data E EEPROM 0 Data E 0
D3 EEPROM 0 Data D EEPROM 0 Data D 0
D2 EEPROM 0 Data C EEPROM 0 Data C 0
D1 EEPROM 0 Data B EEPROM 0 Data B 0
D0 EEPROM 0 Data A EEPROM 0 Data A 0
X 0 0
EEPROM Byte 1 Register
D7
Write Read Default
D6 X 0 0
D5 Non-Muxed Data Non-Muxed Data 0
D4 EEPROM 1 Data E EEPROM 1 Data E 0
D3 EEPROM 1 Data D EEPROM 1 Data D 0
D2 EEPROM 1 Data C EEPROM 1 Data C 0
D1 EEPROM 1 Data B EEPROM 1 Data B 0
D0 EEPROM 1 Data A EEPROM 1 Data A 0
X 0 0
MUX_IN Register
D7
Read
D6 0
D5 0
D4 MUX_IN Data E
D3 MUX_IN Data D
D2 MUX_IN Data C
D1 MUX_IN Data B
D0 MUX_IN Data A
0
If the command byte is a MUX command byte, any additional data bytes sent after the MUX command code will not be acknowledged. If the read/write bit in the address is a logic 1, then a read operation follows and the data sent out depends on the previously stored command code. The MUX_SELECT_1 pin can function as the over-ride pin as on the PCA9559 if the non-volatile register 1 is left at all 0s. The NON_MUXED_OUT pin is a latched output. It is latched when MUX_SELECT_0 = 1. It is transparent when the MUX_SELECT_0 = 0. The data sent out on the NON_MUXED_OUT output is the 6th most significant bit of the non-volatile register. Whether this comes from the non-volatile register 0 or non-volatile register 1 depends on the command code or the external mux-select pins. After a valid I2C write operation to the EEPROM, the part cannot be addressed via the I2C for 3.6 ms. If the part is addressed prior to this time, the part will not acknowledge its address. NOTE: 1. To ensure data integrity, the non-volatile register must be internally write protected when VDD to the I2C bus is powered down or VDD to the component is dropped below normal operating levels.
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Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
CONVERSION FROM THE PCA9559 TO THE PCA9560
The PCA9560 is a drop in replacement to the PCA9559 with no software modifications. The PCA9559 has only one MUX_SELECT pin to choose between the MUX_IN values and the single non-volatile register. Since the PCA9560 has two internal non-volatile registers, if Register 1 is left to all 0's (default condition) then the MUX_SELECT_1 pin can function the same as the PCA9559 OVERRIDE # pin and MUX_SELECT_0 pin can function the same as the PCA9559 MUX_IN pin. The PCA9560 can read the MUX_IN_X values via I2C that the PACA9559 cannot do. Another difference is that the MUX_SELECT_X control pins can be overridden by I2C. To replace the PCA9559 with the PCA9560, the function table for the MUX_OUT outputs and the NON_MUXED_OUT output must stay the same and the MUX_SELECT pin functions should not be overridden by I2C.
EXTERNAL CONTROL SIGNALS
The Write Protect (WP) input is used to control the ability to write the content of the non-volatile registers. If the WP signal is logic 0, the I2C bus will be able to write the contents of the non-volatile registers. If the WP signal is logic 1, data will not be allowed to be written into the non-volatile registers. In this case, the slave address and the command code will be acknowledged but the following data bytes will not be acknowledged and the EEPROM is not updated. The factory default for the contents of the non-volatile register are all logic 0. These stored values can be read or written using the I2C-bus (described in the next section). The WP, MUX_IN*, MUX_SELECT_0, and MUX_SELECT_1 signals have internal pull-up resistors. See the DC and AC Characteristics for hysteresis and signal spike suppression figures.
Function Table1
WP 0 1 X X X X MUX_SELECT_0 X X 0 0 1 1 MUX_SELECT_1 X X 1 0 1 0 COMMANDS Write to the non-volatile registers through I2C bus allowed Write to the non-volatile registers through I2C bus not allowed MUX_OUT and NON_MUXED_OUT (transparent) from EEPROM byte 0 MUX_OUT and NON_MUXED_OUT (transparent) from EEPROM byte 1 MUX_OUT from MUX_IN inputs and NON_MUXED_OUT latched (from EEPROM 0) MUX_OUT from MUX_IN inputs and NON_MUXED_OUT latched (from EEPROM 1)
NOTE: 1. This table is valid when not overridden by I2C control register.
POWER-ON RESET (POR)
When power is applied to VDD, an internal power-on reset holds the PCA9560 in a reset state until VDD has reached VPOR. At that point, the reset condition is released and the PCA9560 volatile registers and I2C/SMBus state machine will initialize to their default states. The MUX_OUT and NON_MUXED_OUT pin values depend on: - the MUX_SELECT_0 and MUX_SELECT_1 logic levels, selecting either the MUX_IN input pins or one of the two 6-bit EEPROMs - the previously stored values in the EEPROM registers/current MUX_IN pin values as shown in the Function Table
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Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
CHARACTERISTICS OF THE I2C-BUS
PCA9560
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 5).
SDA
SCL data line stable; data valid change of data allowed SW00363
Figure 5. Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 6).
System configuration
A device generating a message is a `transmitter', a device receiving is the `receiver'. The device initiates a transfer is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 7).
SDA
SDA
SCL S START condition P STOP condition
SCL
SW00365
Figure 6. Definition of start and stop conditions
SDA SCL
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
I2C MULTIPLEXER
SLAVE SW00366
Figure 7. System configuration
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Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH-level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition 1 2 8 9 clock pulse for acknowledgement SW00368
Figure 8. Acknowledgement on the
I2C-bus
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Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
Bus Transactions
Data is transmitted to the PCA9560 registers using Write Byte transfers (see Figures 9 and 10). Data is read from the PCA9560 registers using Read and Receive Byte transfers (see Figure 11).
slave address
control register write on EEPROM byte 0
EEPROM byte 0 data
S
1
0
0
1
1
A1 A0
0 R/W
A
0
0
0
0
0
0
0
0
A
X
X D5 D4 D3 D2 D1 D0
A
P
stop condition acknowledge from slave acknowledge from slave
start condition
acknowledge from slave
SW00956
Figure 9. WRITE on 1 EEPROM -- assuming WP = 0
slave address
control register write on EEPROM byte 0
EEPROM byte 0 data
EEPROM byte 1 data
S
1
0
0
1
1
A1 A0
0 R/W
A
0
0
0
0
0
0
0
0
A
X
X
D5 D4 D3 D2 D1 D0
A
X
X
D5 D4 D3 D2 D1 D0
A
P
start condition
acknowledge from slave
acknowledge from slave
stop condition
SW00957
Figure 10. WRITE on 2 EEPROMs -- assuming WP = 0
slave address
control register read MUX_IN values
slave address
data from MUX_IN
S
1
0
0
1
1
A1 A0
0 R/W
A
1
1
1
1
1
1
1
1
A
S
1
0
0
1
1
A1 A0
1 R/W
A
0
0
0
4
3
2
1
0
NA
P
restart start condition acknowledge from master acknowledge from master acknowledge from master no acknowledge from master
stop condition SW00958
Figure 11. READ MUX_IN register
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Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL VDD VI VOUT Tstg PARAMETER DC supply voltage DC input voltage DC output voltage Storage temperature range Note 3 Note 3 CONDITIONS RATING -0.5 to +4.6
PCA9560
UNIT V V V C
-1.5 to VDD +1.5 -0.5 to VDD +0.5 -60 to +150
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VDD VIL VIH VOL VIL DC supply voltage LOW-level input voltage HIGH-level input voltage LOW-level output voltage SCL, SDA SCL, SDA SCL, SDA MUX_IN, MUX_SELECT_0, MUX_SELECT_1 MUX_IN, MUX_SELECT_0, MUX_SELECT_1 MUX_OUT, NON_MUXED_OUT MUX_OUT, NON_MUXED_OUT dt/dv Tamb PARAMETER CONDITIONS -- IOL= 3 mA IOL= 3 mA IOL= 3 mA IOL= 6 mA -- LIMITS MIN 3.0 -0.5 2.7 -- -- -0.5 MAX 3.6 0.9 4.0 0.4 0.6 0.8 UNIT V V V V
LOW-level input voltage
V
VIH IOL IOH dt/dv Tamb
HIGH-level input voltage LOW-level output current HIGH-level output current Input transition rise or fall time Operating ambient temperature
-- -- -- -- --
2.0 -- -- 0 -40
4.0 8 100 10 85
V mA A ns/V C
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Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
DC CHARACTERISTICS
LIMITS SYMBOL Supply VDD IDDL IDDH VPOR Supply voltage Supply current Supply current Power-on reset voltage Operating mode ALL inputs = 0 V Operating mode ALL inputs = VDD No load; VI = VDD or GND 3 -- -- -- -- -- -- 2.3 3.6 1 600 2.7 V mA A V PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
Input SCL: Input/Output SDA VIL VIH IOL IOL IIH IIL CI LOW-level input voltage HIGH-level input voltage LOW-level output current LOW-level output current Leakage current HIGH Leakage current LOW Input capacitance VOL = 0.4 V VOL = 0.6 V VI = VDD VI = GND -0.5 2 3 6 -1 -1 -- -- -- -- -- -- -- 3 0.8 VDD + 0.5 -- -- 1 1 6 V V mA mA A A pF
WP, MUX_SELECT_0, MUX_SELECT_1 IIH IIL CI Leakage current HIGH Leakage current LOW Input capacitance VI = VDD VI = GND -1 -20 -- -- -- 2.5 1 -50 5 A A pF
MUX_IN A E IIH IIL CI Leakage current HIGH Leakage current LOW Input capacitance VI = VDD VI = GND -1 -20 -- -- -- 2.5 1 -50 5 A A pF
A0, A1 Inputs IIH IIL CI MUX_OUT VOL VOL IOH LOW-level output voltage LOW-level output voltage HIGH-level output current IOL = 100 A IOL = 4 mA VOH = VDD -- -- -- -- -- -- 0.4 0.7 100 V V A Leakage current HIGH Leakage current LOW Input capacitance VI = VDD VI = GND -1 -20 -- -- -- 2 1 -50 4 A A pF
NON-MUXED_OUT VOL VOL LOW-level output voltage LOW-level output voltage IOL = 100 A IOL = 2 mA -- -- -- -- 0.4 0.7 V V
NON-VOLATILE STORAGE SPECIFICATIONS
PARAMETER Memory cell data retention Number of memory cell write cycles Application Note AN250 2003 Jun 27 I 2C SPECIFICATION 10 years min 100,000 cycles min
DIP Switch provides additional information on memory cell data retention and the minimum number of write cycles. 11
Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
SAC CHARACTERISTICS
SYMBOL MUX_IN MUX_OUT tPLH tPHL tPLH tPHL tR tF CL tPLH tPHL LOW-to-HIGH transition time HIGH-to-LOW transition time LOW-to-HIGH transition time HIGH-to-LOW transition time Output rise time Output fall time Test load capacitance on outputs LOW-to-HIGH transition time HIGH-to-LOW transition time -- -- -- -- 1.0 1.0 -- -- -- 28 8 30 10 -- -- -- 30 9 40 15 43 15 3 3 50 40 15 ns ns ns ns ns/V ns/V pF ns ns PARAMETER LIMITS MIN. TYP. MAX. UNIT
Select MUX_OUT
Select NON-MUXED_OUT
AC SPECIFICATIONS
SYMBOL fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tF tR tSP PARAMETER Operating frequency Bus free time between STOP and START conditions Hold time after (repeated) START condition Repeated START condition setup time Set-up time for STOP condition Data in hold time Valid time for ACK condition2 Data out valid time3 Data set-up time Clock LOW period Clock HIGH period Clock/Data fall time Clock/Data rise time Pulse width of spikes that must be suppressed by the input filters STANDARD MODE I2C-BUS MIN 0 4.7 4.0 4.7 4.0 0 0.3 300 250 4.7 4.0 -- -- -- MAX 100 -- -- -- -- -- 3.45 -- -- -- -- 300 1000 50 FAST MODE I2C-BUS MIN 0 1.3 0.6 0.6 0.6 0 0.1 50 100 1.3 0.6 20 + 0.1 Cb1 20 + 0.1 -- Cb1 MAX 400 -- -- -- -- -- 0.9 -- -- -- -- 300 300 50 kHz s s s s ns s ns ns s s ns ns ns UNITS
NOTES: 1. Cb = total capacitance of one bus line in pF. 2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. 3. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
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Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
SDA
tBUF
tLOW
tR
tF
tHD;STA
tSP
SCL
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
SU00645
Figure 12. Definition of timing
MUX INPUT VM VM VIN PULSE GENERATOR RT
VCC
VO
tPHL
tPLZ
VO
VOUT D.U.T.
RL
MUX OUTPUT
VM VOL + 0.3V VOL
CL
SW00500
Test Circuit for Open Drain Outputs
Figure 13. Open drain output enable and disable times
DEFINITIONS
RL = Load resistor; 1 k CL = Load capacitance includes jig and probe capacitance; 10 pF RT = Termination resistance should be equal to ZOUT of pulse generators.
SW00510
Figure 14. Test circuit
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Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
2003 Jun 27
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Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
2003 Jun 27
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Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
REVISION HISTORY Rev Date _3 20030627
Description Product data (9397 750 11675); ECN 853-2286 29936 dated 19 May 2003. Supersedes data of 2002 May 24 (9397 750 09892). Modifications: * Update marketing information.
* Increase number of write cycles from 3K to 100K.
_2 20020524 Product data (9397 750 09892); ECN 853-2286 28310 of 24 May 2002.
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Philips Semiconductors
Product data
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch
PCA9560
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status[1]
Objective data
Product status[2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 06-03
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 11676
Philips Semiconductors
2003 Jun 27 17

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